1. Field of the Invention
Aspects of the present invention relate to a memory apparatus including a plurality of electrically erasable programmable read-only memories which have the same fixed address, and more particularly, to an apparatus and a method to recognize memory devices in which a signal is output to select a predetermined slave among a plurality of slaves having the same fixed address and a power supply is controlled to supply power only to the selected slave, so that the selected slave can be recognized.
2. Description of the Related Art
When replaceable parts, such as toners and developers, of image forming apparatuses or other apparatuses, including printers, multi-functional peripherals, and copying machines, are used, customer replaceable unit memories (CRUM) are used to manage information on the replaceable parts, including basic information of a product and usage history. Here, the CRUM includes a plurality of electrically erasable programmable read-only memories (EEPROM) having the same fixed address. The CRUMs are identified and recognized independently.
FIG. 1A is a circuit diagram of a conventional apparatus to recognize memory devices.
The conventional apparatus includes a master controller 100, which controls an I2C interface to identify and recognize the plurality of EEPROMs included in the plurality of CRUMs, and a plurality of slaves, which are EEPROMs controlled by the master controller 100. Here, the master controller 100 is connected to a first slave 110 and a second slave 120 in parallel by the I2C bus, which includes VCC, SCL, SDA, and GND terminals.
The I2C bus includes VCC and GND lines which deliver power to the first and the second slaves 110 and 120, an SCL line which delivers a clock signal to synchronize the first and the second slaves 110 and 120 with the master controller 100, and an SDA line which is a data line of the I2C interface as illustrated in FIG. 1C. Here, the master controller 110, at first, transmits a start bit to communicate with the first and the second slaves 110 and 120. Then, the master controller 110 transmits a fixed address corresponding to a slave among a plurality of the slaves with which the master controller 110 wants to communicate. For example, for the first slave 110, the address is ‘000’, and for the second slave 120, the address is ‘001’. Next, the master controller 110 transmits an R/W bit to read/write and then transmits or receives main commands or data to communicate.
In the conventional apparatus, since the first and the second slaves 110 and 120 are implemented in mass-produced replaceable parts, it is difficult and costly for the first and the second slaves 110 and 120 connected to the master controller 100 to have different fixed addresses, as illustrated in FIG. 1A. Therefore, there is a problem of high production cost. If the first and the second slaves 110 and 120 connected to the master controller 100 are configured to have the same fixed address in order to solve this problem, as illustrated in FIG. 1B, there is a problem in that it is impossible to recognize a specific slave and communicate through the existing standard I2C bus.